Since the core of our work is based on LabVIEW, our LabVIEW experts
have decided to share few secret “hacks” we use to work faster, better,
easier and more comfortable. Enjoy the first part of the series and let
us know what you think.
#1 A good looking background makes the work more pleasant
Changing a background is simple, right click on the scroll bar while in the front panel, click on properties and browse your PC for your favorite background. The image you choose will always stay centered and follow the scroll bar as you’re working.
#2 Test a FPGA code
In case you want to test a FPGA code with real-life timing but without real-life signals, using simulated signals, and DMA FIFOs is the solution for you. Testing FPGA logs without real signals using uplink/downlink DMA channels requires you to create an array that is same or similar to the desired signal and send it down to your already written FPGA code using a DMA FIFO. You may read the outputs of your logs via second DMA FIFO. You can also change the timing if you include the Loop Timer Express VI.
#3 Conditional Disable Structures
Have you ever wanted to add a lot of changes to your code for testing but may need them in their previous states? Conditional Disable Structures in LabVIEW will save you tons of time. You can create one or more conditions in your Conditional Disable Structure, and in case where a new update is needed you could add this to the structure and meaning you can always go back to the previous versions.
Did you find these tips useful? Our professional LabVIEW experts have more of these to share, look out for the next article from the series.
#1 A good looking background makes the work more pleasant
Changing a background is simple, right click on the scroll bar while in the front panel, click on properties and browse your PC for your favorite background. The image you choose will always stay centered and follow the scroll bar as you’re working.
#2 Test a FPGA code
In case you want to test a FPGA code with real-life timing but without real-life signals, using simulated signals, and DMA FIFOs is the solution for you. Testing FPGA logs without real signals using uplink/downlink DMA channels requires you to create an array that is same or similar to the desired signal and send it down to your already written FPGA code using a DMA FIFO. You may read the outputs of your logs via second DMA FIFO. You can also change the timing if you include the Loop Timer Express VI.
#3 Conditional Disable Structures
Have you ever wanted to add a lot of changes to your code for testing but may need them in their previous states? Conditional Disable Structures in LabVIEW will save you tons of time. You can create one or more conditions in your Conditional Disable Structure, and in case where a new update is needed you could add this to the structure and meaning you can always go back to the previous versions.
Did you find these tips useful? Our professional LabVIEW experts have more of these to share, look out for the next article from the series.
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